XCF01S Datasheet, PDF (1/47 Pages) Xilinx, Inc – Platform Flash In-System Programmable

47
R
DS123 (v2.13.1) April 3, 2008
0
Platform Flash In-System Programmable
Configuration PROMs
Product Specification
Features
• In-System Programmable PROMs for Configuration of
Xilinx^® FPGAs
• Low-Power Advanced CMOS NOR Flash Process
• Endurance of 20,000 Program/Erase Cycles
• Operation over Full Industrial Temperature Range
(–40°C to +85°C)
• IEEE Standard 1149.1/1532 Boundary-Scan (JTAG)
Support for Programming, Prototyping, and Testing
• JTAG Command Initiation of Standard FPGA
Configuration
• Cascadable for Storing Longer or Multiple Bitstreams
• Dedicated Boundary-Scan (JTAG) I/O Power Supply (V_CCJ)
• I/O Pins Compatible with Voltage Levels Ranging From
1.5V to 3.3V
• Design Support Using the Xilinx Alliance ISE^® and
Foundation™ ISE Series Software Packages
• XCF01S/XCF02S/XCF04S
♦ 3.3V Supply Voltage
♦ Serial FPGA Configuration Interface (up to 33 MHz)
♦ Available in Small-Footprint VO20 and VOG20
Packages
• XCF08P/XCF16P/XCF32P
♦ 1.8V Supply Voltage
♦ Serial or Parallel FPGA Configuration Interface
(up to 33 MHz)
♦ Available in Small-Footprint VO48, VOG48, FS48,
and FSG48 Packages
♦ Design Revision Technology Enables Storing and
Accessing Multiple Design Revisions for
Configuration
♦ Built-In Data Decompressor Compatible with Xilinx
Advanced Compression Technology
Description
Xilinx introduces the Platform Flash series of in-system
programmable configuration PROMs. Available in 1 to 32
Megabit (Mbit) densities, these PROMs provide an easy-to-
use, cost-effective, and reprogrammable method for storing
large Xilinx FPGA configuration bitstreams. The Platform
Flash PROM series includes both the 3.3V XCFxxS PROM
and the 1.8V XCFxxP PROM. The XCFxxS version includes
4-Mbit, 2-Mbit, and 1-Mbit PROMs that support Master
Serial and Slave Serial FPGA configuration modes
(Figure 1, page 2). The XCFxxP version includes 32-Mbit,
16-Mbit, and 8-Mbit PROMs that support Master Serial,
Slave Serial, Master SelectMAP, and Slave SelectMAP
FPGA configuration modes (Figure 2, page 2). A summary
of the Platform Flash PROM family members and supported
features is shown in Table 1.
Table 1: Platform Flash PROM Features
Device
XCF01S
XCF02S
XCF04S
XCF08P
XCF16P
XCF32P
Density V_CCINT V_CCO Range V_CCJ Range
Packages
1 Mbit
2 Mbit
4 Mbit
8 Mbit
16 Mbit
32 Mbit
3.3V
3.3V
3.3V
1.8V
1.8V
1.8V
1.8V – 3.3V 2.5V – 3.3V
1.8V – 3.3V 2.5V – 3.3V
1.8V – 3.3V 2.5V – 3.3V
1.5V – 3.3V 2.5V – 3.3V
1.5V – 3.3V 2.5V – 3.3V
1.5V – 3.3V 2.5V – 3.3V
VO20/VOG20
VO20/VOG20
VO20/VOG20
VO48/VOG48
FS48/FSG48
VO48/VOG48
FS48/FSG48
VO48/VOG48
FS48/FSG48
Program
In-system
via JTAG
3
3
3
Serial
Config.
Parallel
Config.
Design
Revisioning
Compression
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
© 2003–2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United
States and other countries. All other trademarks are the property of their respective owners.
DS123 (v2.13.1) April 3, 2008
www.xilinx.com
Product Specification
1