XCF01S Datasheet, PDF (17/47 Pages) Xilinx, Inc – Platform Flash In-System Programmable

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Platform Flash In-System Programmable Configuration PROMs
X-Ref Target - Figure 7
VCCJ VCCO VCCINT
External ⁽³⁾
Oscillator
VCCO(2)
(1)
VCCINT
D0
V_CCO(2)
VCCJ(2)
Platform Flash
PROM
DIN
MODE PINS⁽¹⁾
Xilinx FPGA
Slave Serial
TDI
TMS
TCK
TDO
TDI
TMS
TCK
GND
CLK⁽³⁾
CE
CEO
OE/RESET
CF⁽⁴⁾
TDO
CCLK
DONE
INIT_B
PROG_B
DOUT
TDI
TMS
TCK
TDO
GND
DIN
CCLK
DONE
INIT_B
PROG_B
...OPTIONAL
Slave FPGAs
with identical
configurations
DIN
CCLK
DONE
INIT_B
PROG_B
...OPTIONAL
Daisy-chained
Slave FPGAs
with different
configurations
Notes:
1 For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet or FPGA
family configuration user guide.
2 For compatible voltages, refer to the appropriate data sheet.
3 In Slave Serial mode, the configuration interface can be clocked by an external oscillator, or optionally—for
the XCFxxP Platform Flash PROM only—the CLKOUT signal can be used to drive the FPGA's
configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal is used, then CLKOUT must be tied to
a 4.7KΩ resistor pulled up to VCCO.
4 For the XCFxxS the CF pin is an output pin. For the XCFxxP the CF pin is a bidirectional pin. For the
XCFxxP, if CF is not connected to PROG_B, then it must be tied to V_CCO via a 4.7 kΩ pull-up resistor.
Figure 7: Configuring in Slave Serial Mode
ds123_12_110707
DS123 (v2.13.1) April 3, 2008
www.xilinx.com
Product Specification
17