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XC5VLX155-1FFG1153I Datasheet, PDF (4/13 Pages) Xilinx, Inc – Virtex-5 Family Overview | |||
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Virtex-5 Family Overview
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Digitally Controlled Impedance (DCI)
Active I/O Termination
⢠Optional series or parallel termination
⢠Temperature and voltage compensation
⢠Makes board layout much easier
â Reduces resistors
â Places termination in the ideal location, at the signal
source or destination
Configuration
⢠Support for platform Flash, standard SPI Flash, or
standard parallel NOR Flash configuration
⢠Bitstream support with dedicated fallback
reconfiguration logic
⢠256-bit AES bitstream decryption provides intellectual
property security and prevents design copying
⢠Improved bitstream error detection/correction capability
⢠Auto bus width detection capability
⢠Partial Reconfiguration via ICAP port
Advanced Flip-Chip Packaging
⢠Pre-engineered packaging technology for proven
superior signal integrity
â Minimized inductive loops from signal to return
â Optimal signal-to-PWR/GND ratios
⢠Reduces SSO induced noise by up to 7x
⢠Pb-Free and standard packages
System Monitor
⢠On-Chip temperature measurement (±4°C)
⢠On-Chip power supply measurement (±1%)
⢠Easy to use, self-contained
â No design required for basic operation
â Autonomous monitoring of all on-chip sensors
â User programmable alarm thresholds for on-chip
sensors
⢠User accessible 10-bit 200kSPS ADC
â Automatic calibration of offset and gain error
â DNL = ±0.9 LSBs maximum
⢠Up to 17 external analog input channels supported
â 0V to 1V input range
â Monitor external sensors e.g., voltage, temperature
â General purpose analog inputs
⢠Full access from fabric or JTAG TAP to System Monitor
⢠Fully operational prior to FPGA configuration and
during device power down (access via JTAG TAP only)
65-nm Copper CMOS Process
⢠1.0V Core Voltage
⢠12-layer metal provides maximum routing capability
and accommodates hard-IP immersion
⢠Triple-oxide technology for proven reduced static power
consumption
System Blocks Specific to the LXT, SXT, TXT, and FXT Devices
Integrated Endpoint Block for PCI Express
Compliance
⢠Works in conjunction with RocketIO GTP transceivers
(LXT and SXT) and GTX transceivers (TXT and FXT)
to deliver full PCI Express Endpoint functionality with
minimal FPGA logic utilization.
⢠Compliant with the PCI Express Base Specification 1.1
⢠PCI Express Endpoint block or Legacy PCI Express
Endpoint block
⢠x8, x4, or x1 lane width
⢠Power management support
⢠Block RAMs used for buffering
⢠Fully buffered transmit and receive
⢠Management interface to access PCI Express
configuration space and internal configuration
⢠Supports the full range of maximum payload sizes
⢠Up to 6 x 32 bit or 3 x 64 bit BARs (or a combination of
32 bit and 64 bit)
Tri-Mode Ethernet Media Access Controller
⢠Designed to the IEEE 802.3-2002 specification
⢠Operates at 10, 100, and 1,000 Mb/s
⢠Supports tri-mode auto-negotiation
⢠Receive address filter (5 address entries)
⢠Fully monolithic 1000Base-X solution with RocketIO
GTP transceivers
⢠Supports multiple external PHY connections (RGMII,
GMII, etc.) interfaces through soft logic and SelectIO
resources
⢠Supports connection to external PHY device through
SGMII using soft logic and RocketIO GTP transceivers
⢠Receive and transmit statistics available through
separate interface
⢠Separate host and client interfaces
⢠Support for jumbo frames
⢠Support for VLAN
⢠Flexible, user-configurable host interface
⢠Supports IEEE 802.3ah-2004 unidirectional mode
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www.xilinx.com
DS100 (v5.0) February 6, 2009
Product Specification
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