|
XC5VLX155-1FFG1153I Datasheet, PDF (1/13 Pages) Xilinx, Inc – Virtex-5 Family Overview | |||
|
0
R
Virtex-5 Family Overview
DS100 (v5.0) February 6, 2009
0
0
Product Specification
General Description
The Virtex®-5 family provides the newest most powerful features in the FPGA market. Using the second generation ASMBL⢠(Advanced
Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choice
offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic
designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks,
including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIO⢠technology with built-in digitally-
controlled impedance, ChipSync⢠source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles
with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options.
Additional platform dependant features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity,
PCI Express® compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance
PowerPC® 440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of
performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5
FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength
of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP
designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and
connectivity capabilities. The Virtex-5 LXT, SXT, TXT, and FXT platforms include advanced high-speed serial connectivity and
link/transaction layer capability.
Summary of Virtex-5 FPGA Features
⢠Five platforms LX, LXT, SXT, TXT, and FXT
â Virtex-5 LX: High-performance general logic applications
â Virtex-5 LXT: High-performance logic with advanced serial
connectivity
â Virtex-5 SXT: High-performance signal processing
applications with advanced serial connectivity
â Virtex-5 TXT: High-performance systems with double
density advanced serial connectivity
â Virtex-5 FXT: High-performance embedded systems with
advanced serial connectivity
⢠Cross-platform compatibility
â LXT, SXT, and FXT devices are footprint compatible in the
same package using adjustable voltage regulators
⢠Most advanced, high-performance, optimal-utilization,
FPGA fabric
â Real 6-input look-up table (LUT) technology
â Dual 5-LUT option
â Improved reduced-hop routing
â 64-bit distributed RAM option
â SRL32/Dual SRL16 option
⢠Powerful clock management tile (CMT) clocking
â Digital Clock Manager (DCM) blocks for zero delay
buffering, frequency synthesis, and clock phase shifting
â PLL blocks for input jitter filtering, zero delay buffering,
frequency synthesis, and phase-matched clock division
⢠36-Kbit block RAM/FIFOs
â True dual-port RAM blocks
â Enhanced optional programmable FIFO logic
â Programmable
- True dual-port widths up to x36
- Simple dual-port widths up to x72
â Built-in optional error-correction circuitry
â Optionally program each block as two independent 18-Kbit
blocks
⢠High-performance parallel SelectIO technology
â 1.2 to 3.3V I/O Operation
â Source-synchronous interfacing using ChipSyncâ¢
technology
â Digitally-controlled impedance (DCI) active termination
â Flexible fine-grained I/O banking
â High-speed memory interface support
⢠Advanced DSP48E slices
â 25 x 18, twoâs complement, multiplication
â Optional adder, subtracter, and accumulator
â Optional pipelining
â Optional bitwise logical functionality
â Dedicated cascade connections
⢠Flexible configuration options
â SPI and Parallel FLASH interface
â Multi-bitstream support with dedicated fallback
reconfiguration logic
â Auto bus width detection capability
⢠System Monitoring capability on all devices
â On-chip/Off-chip thermal monitoring
â On-chip/Off-chip power supply monitoring
â JTAG access to all monitored quantities
⢠Integrated Endpoint blocks for PCI Express Designs
â LXT, SXT, TXT, and FXT Platforms
â Compliant with the PCI Express Base Specification 1.1
â x1, x4, or x8 lane support per block
â Works in conjunction with RocketIO⢠transceivers
⢠Tri-mode 10/100/1000 Mb/s Ethernet MACs
â LXT, SXT, TXT, and FXT Platforms
â RocketIO transceivers can be used as PHY or connect to
external PHY using many soft MII (Media Independent
Interface) options
⢠RocketIO GTP transceivers 100 Mb/s to 3.75 Gb/s
â LXT and SXT Platforms
⢠RocketIO GTX transceivers 150 Mb/s to 6.5 Gb/s
â TXT and FXT Platforms
⢠PowerPC 440 Microprocessors
â FXT Platform only
â RISC architecture
â 7-stage pipeline
â 32-Kbyte instruction and data caches included
â Optimized processor interface structure (crossbar)
⢠65-nm copper CMOS process technology
⢠1.0V core voltage
⢠High signal-integrity flip-chip packaging available in standard
or Pb-free package options
© 2006â2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. PowerPC is a trademark of IBM Corp. and is used under license. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property
of their respective owners.
DS100 (v5.0) February 6, 2009
www.xilinx.com
Product Specification
1
|
▷ |