XC5VLX155-1FFG1153I Datasheet, PDF (12/13 Pages) Xilinx, Inc – Virtex-5 Family Overview

Virtex-5 Family Overview
R
Virtex-5 FPGA Ordering Information
Virtex-5 FPGA ordering information shown in Figure 1 applies to all packages including Pb-Free.
X-Ref Target - Figure 1
Example: XC5VLX50T-1FFG665C
Device Type
Speed Grade
(-1, -2, -3⁽¹⁾)
Note:
1) -3 speed grade is not available in all devices
Temperature Range:
C = Commercial (T_J = 0°C to +85°C)
I = Industrial (T_J = –40°C to +100°C)
Number of Pins
Pb-Free
Package Type
DS100_01_111006
Figure 1: Virtex-5 FPGA Ordering Information
Revision History
The following table shows the revision history for this document.
Date
04/14/06
05/12/06
09/06/06
10/12/06
12/28/06
02/02/07
05/23/07
09/04/07
12/11/07
12/17/07
03/31/08
04/25/08
05/07/08
06/18/08
09/23/08
02/6/09
Version
1.0
1.1
2.0
2.1
2.2
3.0
3.1
3.2
3.3
3.4
4.0
4.1
4.2
4.3
4.4
5.0
Revision
Initial Xilinx release.
First version posted to the Xilinx website. Minor typographical edits and description updates to highlight
new features. Removed LUT utilization bullet from "Virtex-5 FPGA Logic," page 3.
Added LXT platform to entire document. This includes descriptions of the RocketIO GTP transceivers,
the Ethernet MACs, and the PCI Express Endpoint block.
Added LX85T devices. Added System Monitor descriptions and functionality.
Added LX220T devices. Revised the Total I/O banks for the LX330 in Table 1. Revised the
XC5VLX50T-FFG665 example in Figure 1. Clarified support for "Differential SSTL 1.8V and 2.5V
(Class I and II)," page 7.
Added the SXT platform to entire document.
Removed support for IEEE 1149.6
Revised maximum line rate from 3.2 Gb/s to 3.75 Gb/s in entire document.
Added LX20T, LX155T, and LX155 devices.
Added Disclaimer. Revised CMT section on page 3. Clarified "Virtex-5 FPGA LogiCORE Endpoint
Block Plus Wrapper for PCI Express," page 10.
Added FXT platform to entire document.
Clarified information in the following sections: "Integrated Endpoint Block for PCI Express Compliance"
and "Tri-Mode Ethernet Media Access Controller."
To avoid confusion with PLL functionality, removed PMCD references in "Global Clocking," page 8.
Added XC5VSX240T to entire document.
Updated throughout data sheet that the RocketIO GTX transceivers are designed to run from 150 Mb/s
to 6.5 Gb/s.
Clarified PPC440MC_DDR2 memory controller on page 5.
Revised Ethernet MAC column in Table 1, page 2 and added Note 5. Also updated "Tri-Mode
(10/100/1000 Mb/s) Ethernet MACs," page 9.
Added TXT platform to entire document.
Revised RocketIO GTX transciever datapath support on page 10.
Changed document classification to Product Specification from Advance Product Specification.
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DS100 (v5.0) February 6, 2009
Product Specification