DS483 Datasheet, PDF (4/5 Pages) Xilinx, Inc – Configurable size of the input and output bus

Utility Flip-Flop (v1.10a)
Utility Flip-Flop Interrupt Descriptions
There are no interrupts associated with this core.
Utility Flip-Flop Block Diagram
The Utility Bus Flip-Flop block diagram is shown in Figure 2.
X-Ref Target - Figure 2
Set
D(0:C_SIZE-1)
CE
Clk
SET
D
Q
CE
Q(0:C_SIZE-1)
RST
Rst
DS483_02_100609
Figure 2: Utility Bus Split Block Diagram
Design Implementation
Design Tools
The Utility Flip-Flop design is handwritten.
Xilinx XST is the synthesis tool used for synthesizing the Utility Flip-Flop.
Target Technology
The target technology is an FPGA listed in Supported Device Family field of the LogiCORE IP Facts
Table.
Device Utilization and Performance Benchmarks
This core instantiates C_SIZE number of flop-flops.
There are no performance benchmarks available.
Specification Exceptions
Not applicable
Reference Documents
None
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DS483 December 2, 2009
Product Specification