DS483 Datasheet, PDF (3/5 Pages) Xilinx, Inc – Configurable size of the input and output bus

Utility Flip-Flop (v1.10a)
Should the number of values in C_INIT be greater than C_SIZE, the rightmost bits in C_INIT are
ignored. C_INIT greater than one but less than C_SIZE is illegal and will give an error.
Utility Flip-Flop I/O Signals
Table 2: Utility Bus Split I/O Signals
Signal Interface I/O
Description
Clk
None
I
Clock signal
Rst
None
When asynchronous style is selected (C_USE_ASYNCH =1), this signal is
connected as the “reset” signal.
When synchronous style is selected (C_USE_ASYNCH=0), this signal is
connected as the “clear” signal.
I
Rst is active high when active high reset is selected
(C_SET_RST_HIGH=1),
Rst is active low when active low reset is selected (C_SET_RST_HIGH=0)
This signal has no effect when C_USE_RST = 0.
Set
None
When asynchronous style is selected (C_USE_ASYNCH =1), this signal is
connected as the “preset” signal.
When synchronous style is selected (C_USE_ASYNCH=0), this signal is
I
connected as the “set” signal.
Set is active high when active high set is selected (C_SET_RST_HIGH=1),
Set is active low when active low set is selected (C_SET_RST_HIGH=0)
This signal has no effect when C_USE_SET = 0.
CE
None
I
Clock enable.
This signal has no effect when C_USE_CE = 0.
D
None
I
Input data bus to the flip-flop. Bus width is defined by the parameter C_SIZE.
Q
None
O
Output data bus from the flip-flop. Bus width is defined by the parameter
C_SIZE.
Parameter-Port Dependencies
Table 3: Port and Parameter Dependencies
Name
Affects
Depends
Design Parameters
C_SIZE
D
0 to C_SIZE-1
C_SIZE
Q
0 to C_SIZE-1
Port Signals
D
C_SIZE
Q
C_SIZE
Relationship Description
Scale width of input bus
Scale width of output bus
Scale width of input bus
Scale width of output bus
Utility Flip-Flop Register Descriptions
The core implements a pipeline register between the input bus ’D’ and the output bus ’Q’.
DS483 December 2, 2009
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Product Specification