DS483 Datasheet, PDF (1/5 Pages) Xilinx, Inc – Configurable size of the input and output bus

Utility Flip-Flop (v1.10a)
DS483 December 2, 2009
Product Specification
Introduction
The Utility Flip-Flop is a pipelining glue-logic core
intended for use in a Xilinx Platform Studio (XPS)
project.
Features
• Configurable size of the input and output bus
• Supports synchronous set and clear, or
asynchronous reset and preset
• Supports optional clock enable
♦ Programmable init value of the register
LogiCORE™ IP Facts
Core Specifics
Supported Device
Family
Spartan^®-3A/3A DSP, Spartan-3,
Spartan-3E, Automotive
Spartan 3/3E/3A/3A DSP, Spartan-6,
Virtex^®-4 /4Q/4QV, Virtex-5/5FX,
Virtex-6/6CX
Resources Used
Min
Max
LUTs
FFs
0
0
1
Variable ⁽¹⁾
Block RAMs
0
0
Provided with Core
Documentation
Product Specification
Design File Formats VHDL
Constraints File
EDK TCL Generated
Verification
N/A
Instantiation Template EDK
Design Tool Requirements
Xilinx Implementation
Tools
ISE^® 11.4 or later
Verification
ModelSim PE/SE 6.4b or later
Simulation
ModelSim PE/SE 6.4b or later
Synthesis
XST
Support
Provided by Xilinx, Inc.
1. The number of flip-flops equals the parameter C_SIZE.
© 2003-2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
DS483 December 2, 2009
www.xilinx.com
1
Product Specification