DS447 Datasheet, PDF (3/5 Pages) Xilinx, Inc – Data-Side OCM BRAM

Data-Side OCM BRAM (DSBRAM) Interface Controller (v3.00c)
Table 1: Data Side OCM BRAM Interface Controller I/O Signals (Cont’d)
Signal Name
Interface I/O
Description
BRAM_EN_A
BRAM
O BRAM Enable (Port A)
BRAM_WEN_A(0:3)
BRAM
O BRAM Write Enable (Port A)
BRAM_Addr_A(0:31)
BRAM
O BRAM Address (Port A)
BRAM_Din_A(0:31)
BRAM
I BRAM Data Input (Port A)
BRAM_Dout_A(0:31)
BRAM
O BRAM Data Output (Port A)
Note:
1. Bits 0 through 7 are controlled by the parameter C_DSARCVALUE on the Data Side OCM Bus core.
Data Side OCM BRAM Interface Controller Parameters.
Table 2: DSBRAM Interface Controller Parameters
Parameter
Name
Feature/Description
Allowable
Values
Default Value
VHDL Type
C_BASEADDR
DSBRAM Base Address. Automatically
calculated by the EDK tools. The most
significant 8 bits of the Base Address
correspond to the DSOCM Address
Range Compare Value
(C_DSARCVALUE) parameter of the
Data Side OCM Bus core.
Valid
Address
Range ¹
0xFFFFFFFF ²
std_logic_vector
(0 to 31)
C_HIGHADDR
DSBRAM HIGH Address. Automatically
calculated by the EDK tools.
Valid
Address
Range ¹
0x00000000 ²
std_logic_vector
(0 to 31)
Constant enable of BRAM. Improves
C_BRAM_EN BRAM access time while increasing
0, 1
0
static power dissipation when set to 1.
integer
Enable address range checking. When
used on a multi-slave data-side OCM
bus, this parameter must be set to 1. It
enforces strict address range checking
for the address space declared for this
C_RANGE
CHECK
controller. On a single slave bus, the
parameter can be set to 0 to save logic, 0, 1
however this will result in a wrap-around
0
effect when data-side OCM addresses
outside the defined range are used: data
accessed on address 0 is the same as
that accessed on address 2ⁿ, for a
memory controller of 2ⁿ bytes.
integer
Note:
1. The range specified by C_BASEADDR and C_HIGHADDR must be a complete, contiguous power-of-two range,
with a maximum size of 16MB. C_BASEADDR must be a multiple of the range, where the range is C_HIGHADDR
- C_BASEADDR +1. The 16 MB address space overlaps that of the Processor Local Bus (PLB) and cannot be used
by PLB peripherals. All peripherals must reside in the same 16 MB space.
2. Default value specified for C_BASEADDR and C_HIGHADDR is used to ensure that an actual value is set; if the
value is not set, a compiler error is generated.
DS447 June 24, 2009
www.xilinx.com
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Product Specification