DS447 Datasheet, PDF (1/5 Pages) Xilinx, Inc – Data-Side OCM BRAM

DS447 June 24, 2009
Data-Side OCM BRAM (DSBRAM)
Interface Controller (v3.00c)
Product Specification
Introduction
The Data-Side OCM BRAM (DSBRAM) Interface
Controller connects a BRAM Block to the data-side on-
chip memory (DSOCM) bus in a PowerPC^® 405-based
embedded systems processor. For information about
the DSOCM controller interface, see the PowerPC 405
Processor Block Reference Guide.
The DSBRAM (v3.00c) Interface Controller core is used
with the Data Side OCM Bus v10 (v2.00b).
Features
• Supports byte, half-word, and word transfers
• Configurable address decoding for use on multi-
slave DSOCM buses
• Configurable permanent BRAM enable for
improved performance
LogiCORE™ IP Facts
Core Specifics
Supported Device
Family
Virtex®-4 FX
Version of Core
dsbram_if_cntrl
v3.00c
Resources Used
Min
Max
Slices
LUTs
N/A
N.A.
0
9¹
FFs
0
0
Block RAMs
0
0
Provided with Core
Documentation
Product Specification
Design File Formats
VHDL
Constraints File
N/A
Verification
N/A
Instantiation Template
N/A
Reference Designs
N/A
Design Tool Requirements
Xilinx® Implementation
Tools
ISE® v11.1 software
Verification
N/A
Simulation
Mentor Graphics ModelSim v6.4b
and above
Synthesis
XST
Support
Provided by Xilinx, Inc.
Note: Address decoding logic when configured for multi-slave use.
Less logic required for larger address range
© 2004-2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. All other trademarks are the property of their respective
owners.
DS447 June 24, 2009
www.xilinx.com
1
Product Specification