DS447 Datasheet, PDF (2/5 Pages) Xilinx, Inc – Data-Side OCM BRAM

Data-Side OCM BRAM (DSBRAM) Interface Controller (v3.00c)
Functional Description
The block diagram and signals for the Data-Side OCM (DSBRAM) Interface Controller are shown in
Figure 1. The signal names for the core are listed and described in Table 1.
Figure Top x-ref 1
BRAMDSOCMCLK
DSBRAMRST
To and from
DSOCM_V10_bus
DSOCMBRAMBYTEWRITE(0:3)
DSOCMBRAMN
DSOCMBRAMABUS(8:29)
DSOCMBRAMWRDBUS(0:31)
S_BRAMDSOCMRDDBUS(0:31)
S_DSOCMRWCOMPLETE
Data Side
OCM BRAM
Interface Controller
To and from
BRAM_Block_port
BRAM_Clk_A
BRAM_Rst_A
BRAM_EN_A
BRAM_WEN_A(0:31)
BRAM_Addr_A(0:31)
BRAM_Din_A(0:31)
BRAM_Dout_A(0:31)
S_DSOCMSLAVESELECT
ds447_01
Figure 1: Data Side OCM BRAM Interface Controller Block Diagram
Data Side OCM BRAM Interface Controller I/O Signals
Table 1: Data Side OCM BRAM Interface Controller I/O Signals
Signal Name
Interface I/O
Description
BRAMDSOCMCLK
DSOCM
I
This signal is passed to the BRAM_Clk_A output,
which can be used as clock to the BRAM.
DSBRAMRST
DSOCM
This signal is passed to the BRAM_Rst_A output,
I which can be used as reset to the BRAM. (Active
High)
DSOCMBRAMBYTEWRITE (0:3)
DSOCM
I DSBRAM Byte Enable from PowerPC405 processor
DSOCMBRAMEN
DSOCMBRAMABUS(8:29) ¹
DSOCM
DSOCM
I DSBRAM Enable from PowerPC405 processor
I DSBRAM Address Bus from PowerPC405 processor
DSOCMBRAMWRDBUS (0:31)
DSOCM
I
DSBRAM Write Data Bus from PowerPC405
processor
S_BRAMDSOCMRDDBUS (0:31) DSOCM O DSBRAM Read Data Bus to PowerPC405 processor
S_DSOCMRWCOMPLETE
DSOCM
O
Handshake signal for variable latency access in
Virtex-4 devices.
S_DSOCMSLAVESELECT
DSOCM
Data valid signal used to qualify read-data from the
O controller in a multi-slave system
(C_RANGECHECK=1)
BRAM_Rst_A
BRAM
O BRAM Reset (Port A)
BRAM_Clk_A
BRAM
O BRAM Clock (Port A)
2
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DS447 June 24, 2009
Product Specification