X40010 Datasheet, PDF (9/25 Pages) Xicor Inc. – Dual Voltage Monitor with Integrated CPU Supervisor

X40010/X40011/X40014/X40015 – Preliminary
Figure 7. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Serial Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. See Figure 8.
The device will respond with an acknowledge after rec-
ognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave
Address Byte. If a write operation is selected, the
device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for the Slave Address Byte when the Device
Identifier and/or Select bits are incorrect.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
Figure 8. Acknowledge Response From Receiver
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
Serial Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and a Word Address Byte. This gives the
master access to any one of the words in the array.
After receipt of the Word Address Byte, the device
responds with an acknowledge, and awaits the next
eight bits of data. After receiving the 8 bits of the Data
Byte, the device again responds with an acknowledge.
The master then terminates the transfer by generating
a stop condition, at which time the device begins the
internal write cycle to the nonvolatile memory. During
this internal write cycle, the device inputs are disabled, so
the device will not respond to any requests from the mas-
ter. The SDA output is at high impedance. See Figure 9.
A write to a protected block of memory will suppress
the acknowledge bit.
SCL from
Master
1
Data Output
from Transmitter
8
9
Data Output
from Receiver
Start
Acknowledge
REV 1.3.4 7/12/02
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Characteristics subject to change without notice. 9 of 25