X40010 Datasheet, PDF (12/25 Pages) Xicor Inc. – Dual Voltage Monitor with Integrated CPU Supervisor

X40010/X40011/X40014/X40015 – Preliminary
SERIAL DEVICE ADDRESSING
Memory Address Map
CR, Control Register, CR7: CR0
Address: 1FF_hex
FDR, Fault DetectionRegister, FDR7: FDR0
Address: 0FF_hex
Slave Address Byte
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
– a device type identifier that is always ‘101x’. Where
x=0 is for Array, x=1 is for Control Register or Fault
Detection Register.
– next two bits are ‘0’.
– next bit that becomes the MSB of the address.
Figure 11. X40010/11/14/15 Addressing
Slave Byte
Control Register
1 0 1 1 0 0 1 R/W
Fault Detection Register 1 0 1 1 0 0 _{0 R/W}
Word Address
Control Register
111 11111
Fault Detection Register _{1 1 1 1 1 1 1 1}
Figure 12. Current Address Read Sequence
.
S
Signals from
the Master
t
a
r
Slave
Address
S
t
o
t
p
SDA Bus
10 1000 1
Signals from
the Slave
Data
Figure 13. Random Address Read Sequence
S
S
Signals from ^t
Slave
the Master
a
r
Address
Byte
Address
t
Slave
a _Address
r
S
t
o
t
t
p
SDA Bus
101 00 0
1
Signals from
the Slave
A
A
C
C
K
K
A
C
K
Data
REV 1.3.4 7/12/02
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Characteristics subject to change without notice. 12 of 25