X28HC64 Datasheet, PDF (9/24 Pages) Xicor Inc. – 5 Volt, Byte Alterable E2PROM

X28HC64
SYSTEM CONSIDERATIONS
Because the X28HC64 is frequently used in large memory
arrays, it is provided with a two line control architecture
for both read and write operations. Proper usage can
provide the lowest possible power dissipation and elimi-
nate the possibility of contention where multiple I/O pins
share the same bus.
To gain the most benefit it is recommended that CE be
decoded from the address bus and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation, this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.
Because the X28HC64 has two power modes, standby
and active, proper decoupling of the memory array is of
Normalized I_CC(RD) by Temperature
Over Frequency
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
5.5 VCC
- 55°C
+ 25°C
+ 125°C
10
FREQUENCY (MHz)
20
3857 FHD F20.1
prime concern. Enabling CE will cause transient current
spikes. The magnitude of these spikes is dependent on
the output capacitive loading of the I/Os. Therefore, the
larger the array sharing a common bus, the larger the
transient spikes. The voltage peaks associated with the
current transients can be suppressed by the proper
selection and placement of decoupling capacitors. As a
minimum, it is recommended that a 0.1µF high fre-
quency ceramic capacitor be used between V_CC and
V_SS at each device. Depending on the size of the array,
the value of the capacitor may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between V_CC and V_SS for each
eight devices employed in the array. This bulk capacitor
is employed to overcome the voltage droop caused by
the inductive effects of the PC board traces.
Normalized I_CC(RD) @ 25% Over
the V_CC Range and Frequency
1.4
1.2
5.5 VCC
5.0 VCC
1.0
4.5 VCC
0.8
0.6
0.4
0.2
0
10
FREQUENCY (MHz)
20
3857 FHD F21.1
9