X9521 Datasheet, PDF (8/26 Pages) Xicor Inc. – Dual DCP, EEPROM Memory

X9521 – Preliminary Information
Signals from
the Master
SDA Bus
Signals from
the Slave
WRITE Operation
READ Operation
S
S
t
a
r
Slave
Address
Instruction
Byte
t
a
Slave
r ^Address
S
t
Data Byte o
t
t
p
10101110
W
T
00000
P
1
P
0
10101111
A
A
A
C
C
C
K
K
K
“Dummy” write
Figure 10. DCP Read Sequence
DCPx
-
x=1
MSB
LSB
“-” = DON’T CARE
x=2
“wiper terminal” to tap position 28. The mapping of the
Data Byte to “wiper position” data for DCP1 (100 Tap), is
shown in “APPENDIX 1” . An example of a simple C lan-
guage function which “translates” between the tap posi-
tion (decimal) and the Data Byte (binary) for DCP1, is
given in “APPENDIX 2” .
It should be noted that all writes to any DCP of the X9521
are random in nature. Therefore, the Data Byte of consec-
utive write operations to any DCP can differ by an arbi-
trary number of bits. Also, setting the bits (P1=0, P0=0) or
(P1=1, P0=1) are reserved sequences, and will result in
no ACKNOWLEDGE after sending an Instruction Byte on
SDA.
The factory default setting of all “wiper position” settings is
with 00h stored in the NVM of the DCPs. This corre-
sponds to having the “wiper teminal” R_WX (x=1,2) at the
“lowest” tap position, Therefore, the resistance between
R_WX and R_LX is a minimum (essentially only the Wiper
Resistance, R_W).
DCP Read Operation
A read of DCPx (x=1,2) can be performed using the three
byte random read command sequence shown in Figure
10.
The master issues the START condition and the Slave
Address Byte 10101110 which specifies that a “dummy”
write” is to be conducted. This “dummy” write operation
sets which DCP is to be read (in the preceding Read
operation). An ACKNOWLEDGE is returned by the
X9521 after the Slave Address if received correctly. Next,
an Instruction Byte is issued on SDA. Bits P1-P0 of the
Instruction Byte determine which DCP “wiper position” is
to be read. In this case, the state of the WT bit is “don’t
care”. If the Instruction Byte format is valid, then another
ACKNOWLEDGE is returned by the X9521.
Following this ACKNOWLEDGE, the master immediately
issues another START condition and a valid Slave
address byte with the R/W bit set to 1. Then the X9521
issues an ACKNOWLEDGE followed by Data Byte, and
Signals from
the Master
S
t
WRITE Operation
a
r
Slave
Address
t _Address
Byte
S
t
Data
o
Byte
p
SDA Bus
101 00 000
Signals from
the Slave
A
A
A
Internal _C
C
C
Device
Address
K
K
K
Figure 11. EEPROM Byte Write Sequence
REV 1.1.9 1/30/03
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Characteristics subject to change without notice. 8 of 26