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X9521 Datasheet, PDF (4/26 Pages) Xicor Inc. – Dual DCP, EEPROM Memory | |||
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X9521 â Preliminary Information
SCL
from
1
Master
Data Output
from
Transmitter
8
9
Data Output
from
Receiver
Start
Acknowledge
Figure 3. Acknowledge Response From Receiver
nate further data transmissions if an ACKNOWLEDGE is
not detected. The master must then issue a STOP condi-
tion to place the device into a known state.
DEVICE INTERNAL ADDRESSING
Addressing Protocol Overview
The user addressable internal components of the X9521
can be split up into three main parts:
âTwo Digitally Controlled Potentiometers (DCPs)
âEEPROM array
âControl and Status (CONSTAT) Register
Depending upon the operation to be performed on each
of these individual parts, a 1, 2 or 3 Byte protocol is used.
All operations however must begin with the Slave Address
Byte being issued on the SDA pin. The Slave address
selects the part of the X9521 to be addressed, and speci-
ï¬es if a Read or Write operation is to be performed.
It should be noted that in order to perform a write opera-
tion to either a DCP or the EEPROM array, the Write
Enable Latch (WEL) bit must ï¬rst be set (See âBL1, BL0:
Block Lock protection bits - (Nonvolatile)â on page 12.)
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4.). This byte con-
sists of three parts:
âThe Device Type Identiï¬er which consists of the most
signiï¬cant four bits of the Slave Address (SA7 - SA4).
The Device Type Identiï¬er must always be set to 1010
in order to select the X9521.
âThe next three bits (SA3 - SA1) are the Internal Device
Address bits. Setting these bits to 000 internally selects
the EEPROM array, while setting these bits to 111
selects the DCP structures in the X9521. The CON-
STAT Register may be selected using the Internal
Device Address 010.
âThe Least Signiï¬cant Bit of the Slave Address (SA0)
Byte is the R/W bit. This bit deï¬nes the operation to be
performed on the device being addressed (as deï¬ned
in the bits SA3 - SA1). When the R/W bit is â1â, then a
READ operation is selected. A â0â selects a WRITE
operation (Refer to Figure 4.)
SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
101 0
R/W
DEVICE TYPE
IDENTIFIER
INTERNAL
DEVICE
ADDRESS
READ /
WRITE
Internal Address
(SA3 - SA1)
000
010
111
Internally Addressed
Device
EEPROM Array
CONSTAT Register
DCP
Bit SA0
0
1
Operation
WRITE
READ
Figure 4. Slave Address Format
REV 1.1.9 1/30/03
www.xicor.com
Characteristics subject to change without notice. 4 of 26
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