X9521 Datasheet, PDF (5/26 Pages) Xicor Inc. – Dual DCP, EEPROM Memory

X9521 – Preliminary Information
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence (for either
the EEPROM array, the Non Volatile Memory of a DCP
(NVM), or the CONSTAT Register) has been correctly
issued (including the final STOP condition), the X9521 ini-
tiates an internal high voltage write cycle. This cycle typi-
cally requires 5 ms. During this time, no further Read or
Write commands can be issued to the device. Write
Acknowledge Polling is used to determine when this high
voltage write cycle has been completed.
To perform acknowledge polling, the master issues a
START condition followed by a Slave Address Byte. The
Slave Address issued must contain a valid Internal Device
Address. The LSB of the Slave Address (R/W) can be set
to either 1 or 0 in this case. If the device is still busy with
the high voltage cycle then no ACKNOWLEDGE will be
returned. If the device has completed the write operation,
an ACKNOWLEDGE will be returned and the host can
then proceed with a read or write operation. (Refer to Fig-
ure 5.).
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
Issue Slave Address
Byte (Read or Write)
Issue STOP
ACK
returned?
YES
High Voltage Cycle
complete. Continue
command sequence?
NO
NO
YES
Continue normal
Read or Write
command sequence
Issue STOP
PROCEED
Figure 5. Acknowledge Polling Sequence
N
R_Hx
WIPER
COUNTER
REGISTER
(WCR)
NON
VOLATILE
MEMORY
(NVM)
DECODER
2
1
0
“WIPER”
FET
SWITCHES
RESISTOR
ARRAY
R_Lx
R_Wx
Figure 6. DCP Internal Structure
DIGITALLY CONTROLLED POTENTIOMETERS
DCP Functionality
The X9521 includes two independent resistor arrays.
These arrays respectively contain 99 and 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R_Hx and R_Lx
inputs - where x = 1,2).
At both ends of each array and between each resistor
segment there is a CMOS switch connected to the wiper
(R_wx) output. Within each individual array, only one switch
may be turned on at any one time. These switches are
controlled by the Wiper Counter Register (WCR) (See
Figure 6). The WCR is a volatile register.
On power up of the X9521, wiper position data is auto-
matically loaded into the WCR from its associated Non
Volatile Memory (NVM) Register. The Table below shows
the Initial Values of the DCP WCR’s before the contents of
the NVM is loaded into the WCR.
DCP
R₁ / 100 TAP
R₂ / 256 TAP
Initial Values Before Recall
V_L / TAP = 0
V_H / TAP = 255
The data in the WCR is then decoded to select and
enable one of the respective FET switches. A “make
REV 1.1.9 1/30/03
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Characteristics subject to change without notice. 5 of 26