X76F100 Datasheet, PDF (7/17 Pages) Xicor Inc. – 1K 128 x 8 Bit

X76F100
PASSWORDS
Passwords are changed by sending the “change read
password” or “change write password” commands in a
normal sector write operation. A full eight bytes con-
taining the new password must be sent, following suc-
cessful transmission of the current write password and
a valid password ACK response. The user can use a
repeated ACK Polling command to check that a new
password has been written correctly. An ACK indicates
that the new password is valid.
There is no way to read any of the passwords.
Response to Reset (Default = 19 00 AA 55)
The ISO Response to reset is controlled by the RST,
CS and CLK pins. When RST is pulsed high, while CS
is low, the device will output 32-bits of data, one bit per
clock. This conforms to the ISO standard for “synchro-
nous response to reset”. CS must remain LOW and the
part must not be in a write cycle for the response to
reset to occur.
After initiating a nonvolatile write cycle the RST pin
must not be pulsed until the nonvolatile write cycle is
complete. If not, the ISO response will not be acti-
vated. Also, any attempt to pulse the RST pin in the
middle of an ISO transaction will stop the transaction
with the SDA pin in high impedance. The user will have
to issue a stop condition and start the transaction
again. If at any time during the Response to Reset CS
goes HIGH, the response to reset will be aborted and
the part will return to the standby state. A Response to
Reset is not available during a nonvolatile write cycle.
Continued clocks after the 32-bits, will output the 32-bit
sequence again, starting at byte 0.
Figure 7. Response to RESET(RST)
CS
RST
SCK
SO
1 0 0 11 0 0 0 0 0 0 00 0 0 0 0 10 1 ⁰ 1 ⁰ 1 101 0 1 0 1 0
LSB
Byte
MSB LSB
0
MSB LSB
1
MSB LSB
2
MSB
3
REV 1.0 6/22/00
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Characteristics subject to change without notice. 7 of 16