X24F064 Datasheet, PDF (7/18 Pages) Xicor Inc. – SerialFlash TM Memory with Block Lock TM Protection

X24F064/032/016
Current Address Read
Internally, the X24F064/032/016 contains an ad-
dress counter that maintains the address of the last
byte read, incremented by one byte. Therefore, if the
last read was from address n, the next read opera-
tion accesses data from address n + 1. Upon receipt
of the slave address with the R/W set HIGH, the
X24F064/032/016 issues an acknowledge and trans-
mits the eight-bit word. The read operation is termi-
nated by the master; by not responding with an
acknowledge and by issuing a stop condition. Refer
to Figure 6 for the sequence of address, acknowl-
edge and data transfer.
Random Read
Random read operations allow the master to access
any memory location in a random manner. Prior to is-
suing the slave address with the R/W bit set HIGH, the
master must first perform a “dummy” write operation.
The master issues the start condition, and the slave ad-
dress with the R/W bit set LOW, followed by the byte
address it is to read. After the byte address acknowl-
edge, the master immediately reissues the start condi-
tion and the slave address with the R/W bit set HIGH.
This will be followed by an acknowledge from the
X24F064/032/016 and then by the eight-bit byte. The
read operation is terminated by the master; by not re-
sponding with an acknowledge and by issuing a stop
condition. Refer to Figure 7 for the address, acknowl-
edge and data transfer sequence.
Figure 6. Current Address Read
S
BUS ACTIVITY:
MASTER
T
A
R
SLAVE
ADDRESS
T
SDA LINE
S
A
BUS ACTIVITY:
C
X24F016/032/064
K
S
T
O
P
P
DATA
6686 ILL F11.1
Figure 7. Random Read
BUS ACTIVITY:
MASTER
S
T
A
R
SLAVE
ADDRESS
T
BYTE
ADDRESS n
S
T
A
R
SLAVE
ADDRESS
T
SDA LINE
S
S
BUS ACTIVITY:
X24F016/032/064
A
A
A
C
C
C
K
K
K
S
T
O
P
P
DATA n
6686 ILL F12.3
7