X24F064 Datasheet, PDF (3/18 Pages) Xicor Inc. – SerialFlash TM Memory with Block Lock TM Protection

X24F064/032/016
DEVICE OPERATION
The X24F064/032/016 supports a bidirectional bus ori-
ented protocol. The protocol defines any device that
sends data onto the bus as a transmitter, and the re-
ceiving device as the receiver. The device controlling
the transfer is a master and the device being controlled
is the slave. The master will always initiate data trans-
fers, and provide the clock for both transmit and receive
operations. Therefore, the X24F064/032/016 will be
considered a slave in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24F064/032/016 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition has
been met.
Figure 1. Data Validity
SCL
SDA
DATA STABLE DATA
CHANGE
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Notes: (5) Typical values are for T_A = 25°C and nominal supply voltage (2.7V)
(6) t_PR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the
device requires to perform the internal program operation.
Figure 2. Definition of Start and Stop
SCL
SDA
START BIT
STOP BIT
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3