X40626 Datasheet, PDF (2/23 Pages) Xicor Inc. – Dual Voltage CPU Supervisor with 64K Serial EEPROM

X40626
operating level and stabilizes. Four industry standard Vtrip
thresholds are available. However, Xicor’s unique circuits
allow the threshold to be reprogrammed to meet custom
requirements or to fine-tune the threshold for applications
requiring higher precision.
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s Block Lock^™ Protection. The
array is internally organized as 64 bytes per page. The
device features an 2-wire interface and software protocol
allowing operation on an I²C bus.
The device utilizes Xicor’s proprietary Direct Write^™ cell,
providing a minimum endurance of 100,000 page write
cycles and a minimum data retention of 100 years.
PIN CONFIGURATION
14 Pin SOIC/TSSOP
NC 1
S₀ 2
S₁ 3
NC 4
RESET 5
NC ⁶
V_SS 7
14 V_CC
13 NC
12 WP
11 V2MON
10 V2FAIL
9 SCL
8 SDA
PIN FUNCTION
Pin
1, 4, 6, 13
2
3
5
Name
NC
S₀
S₁
RESET
7
V_SS
8
SDA
9
SCL
10
V2FAIL
11
V2MON
12
WP
14
V_CC
Function
No Internal Connections
Device Select Input
Device Select Input
Reset Output. RESET is an active LOW, open drain output which goes active whenever V_CC
falls below the minimum V_CC sense level. It will remain active until V_CC rises above the min-
imum V_CC sense level for typically 200ms. RESET goes active if the Watchdog Timer is
enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time-
out period. A falling edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET
goes active on power up and remains active for typically 200ms after the power supply
stabilizes.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has
an open drain output and may be wire ORed with other open drain or open collector outputs.
This pin requires a pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts the
Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time-out
period results in RESET going active.
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than
V_TRIP2 and goes HIGH when V2MON exceeds V_TRIP2. There is no power up reset delay
circuitry on this pin. This circuit works independently from the Low V_CC reset and battery
switch circuits. Connect V2FAIL to VSS when not used.
V2 Voltage Monitor Input. When the V2MON input is less than the V_TRIP2 voltage, V2FAIL
goes LOW. This input can monitor an unregulated power supply with an external resistor
divider or can monitor a second power supply with no external components. Connect
V2MON to V_SS or V_CC when not used. There is no hysteresis in the V2MON comparator
circuits.
Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to the control
register.
Supply Voltage
REV 1.1.15 2/11/04
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Characteristics subject to change without notice. 2 of 23