X40626 Datasheet, PDF (10/23 Pages) Xicor Inc. – Dual Voltage CPU Supervisor with 64K Serial EEPROM

X40626
Figure 9. Page Write Operation
S
Signals from
the Master
T
A
R
Slave
Address
T
Word Address
Byte 1
Word Address
Byte 0
Data
(0)
SDA Bus ^{S 1 0 1 0 0 S}1^S0 ⁰
Signals from
the Slave
A
A
A
A
C
C
C
C
K
K
K
K
(I ≤ n ≤ 63)
Data
S
(n)
T
O
P
P
A
C
K
Figure 10. Writing 12 bytes to a 64-byte page starting at location 60 (Wrap around).
8 Bytes
address
=7
address pointer
ends here
Addr = 8
address
60
4 Bytes
address
63
The master terminates the Data Byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. See Figure 9 for the address, acknowledge,
and data transfer sequence.
Stops and Write Modes
Stop conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte
plus the subsequent ACK signal. If a stop is issued in
the middle of a data byte, or before 1 full data byte plus
its associated ACK is sent, then the device will reset
itself without performing the write. The contents of the
array will not be effected.
Acknowledge Polling
The disabling of the inputs during nonvolatile cycles
can be used to take advantage of the typical 5mS write
cycle time. Once the stop condition is issued to indicate
the end of the master’s byte load operation, the device
initiates the internal nonvolatile cycle. Acknowledge
polling can be initiated immediately. To do this, the
master issues a start condition followed by the Slave
Address Byte for a write or read operation. If the device
is still busy with the nonvolatile cycle then no ACK will
be returned. If the device has completed the write oper-
ation, an ACK will be returned and the host can then
proceed with the read or write operation. Refer to the
flow chart in Figure 11.
REV 1.1.15 2/11/04
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Characteristics subject to change without notice. 10 of 23