X40626 Datasheet, PDF (11/23 Pages) Xicor Inc. – Dual Voltage CPU Supervisor with 64K Serial EEPROM

X40626
Figure 11. Acknowledge Polling Sequence
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
Issue Slave Address
Byte (Read or Write)
Issue STOP
ACK
returned?
YES
Nonvolatile Cycle
complete. Continue
command sequence?
NO
NO
Issue STOP
YES
Continue Normal
Read or Write
Command Sequence
PROCEED
Serial Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power up, the address in the
address counter is 00H.
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the Data Byte. The mas-
ter terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. Refer to Figure 12 for
the address, acknowledge, and data transfer
sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during the
ninth clock cycle and then issue a stop condition.
Figure 12. Current Address Read Sequence
S
Signals from
the Master
t
a
r
Slave
Address
S
t
o
t
p
SDA Bus
1 0 1 0 0 S₁ S₀ 1
Signals from
the Slave
A
C
K
Data
REV 1.1.15 2/11/04
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Characteristics subject to change without notice. 11 of 23