X25F128 Datasheet, PDF (2/14 Pages) Xicor Inc. – SerialFlash™ Memory With Block Lock™ Protection

X25F128
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push-pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of the
serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.
Chip Select (CS)
When CS is HIGH, the X25F128 is deselected and the
SO output pin is at high impedance and unless an
internal program operation is underway the X25F128
will be in the standby power mode. CS LOW enables
the X25F128, placing it in the active power mode. It
should be noted that after power-up, a HIGH to LOW
transition on CS is required prior to the start of any
operation.
Program Protect (PP)
When PP is LOW and the nonvolatile bit PPEN is “1”,
nonvolatile programming of the X25F128 status register
is disabled, but the part otherwise functions normally.
When PP is held HIGH, all functions, including nonvola-
tile programming operate normally. PP going LOW while
CS is still LOW will interrupt programming of the
X25F128 status register. If the internal program cycle
has already been initiated, PP going LOW will have no
effect on programming.
The PP pin function is blocked when the PPEN bit in
the status register is “0”. This allows the user to install the
X25F128 into a system with PP pin grounded and still
be able to program the status register. The PP pin
functions will be enabled when the PPEN bit is set “0”.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence
is underway, HOLD may be used to pause the serial
communication with the controller without resetting the
serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH
at all times.
PIN CONFIGURATION
CS
SO
PP
VSS
8-LEAD DIP
1
8
2
7
X25F128
3
6
4
5
VCC
HOLD
SCK
SI
CS
SO
NC
NC
NC
NC
PP
VSS
16-LEAD SOIC
1
16
2
15
3
14
4
13
X25F128
5
12
6
11
7
10
8
9
VCC
HOLD
NC
NC
NC
NC
SCK
SI
6829 ILL F02.1
PIN NAMES
SYMBOL
CS
SO
SI
SCK
PP
VSS
VCC
HOLD
NC
DESCRIPTION
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Program Protect Input
Ground
Supply Voltage
Hold Input
No Connect
6829 PGM T01
2