WM8778 Datasheet, PDF (8/50 Pages) Wolfson Microelectronics plc – 24 BIT 192KHZ STEREO CODEC

WM8778
MASTER CLOCK TIMING
MCLK
t_MCLKL
t_MCLKH
t_MCLKY
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Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25^oC, fs = 48kHz, ADC/DACMCLK = 256fs unless otherwise
stated.
PARAMETER
SYMBOL
System Clock Timing Information
ADC/DACMCLK System clock
pulse width high
tMCLKH
ADC/DACMCLK System clock
pulse width low
tMCLKL
ADC/DACMCLK System clock
cycle time
tMCLKY
ADC/DACMCLK Duty cycle
Table 1 Master Clock Timing Requirements
TEST CONDITIONS
MIN
11
11
28
40:60
TYP
MAX
UNIT
ns
ns
ns
60:40
DIGITAL AUDIO INTERFACE – MASTER MODE
DACBCLK
ADCBCLK
ADCLRC
WM8778
CODEC _DACLRC
DOUT
DIN
DVD
Controller
Figure 2 Audio Interface - Master Mode
w
PP Rev 1.7 June 2004
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