WM8778 Datasheet, PDF (21/50 Pages) Wolfson Microelectronics plc – 24 BIT 192KHZ STEREO CODEC

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WM8778
The MSB of the left channel ADC data is output on DOUT and changes on the same falling edge of
ADCBCLK as the low to high ADCLRC transition and may be sampled on the rising edge of
ADCBCLK. The right channel ADC data is contiguous with the left channel data (Figure 18).
1/fs
ADCLRC
ADCBCLK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DOUT
12
n-1 n 1 2
n-1 n
1
MSB
LSB
Word Length (WL)
Figure 18 DSP Late Mode Timing Diagram – ADC Data Output
In both early and late DSP modes, the left channel is always sent first, followed immediately by the
right channel. No DACBCLK edges are allowed between the data words.
CONTROL INTERFACE OPERATION
The WM8778 is controlled by writing to registers through a serial control interface. A control word
consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is
accessed. The remaining 9 bits (B8 to B0) are data bits, corresponding to the 9 bits in each control
register. The control interface can operate as either a 3-wire or 2-wire MPU interface. The MODE pin
selects the interface format, as shown in Table 10.
MODE
CONTROL MODE
0
Z / midrail
1
2 wire software
Hardware
3 wire software
Table 10 Control Interface Selection via MODE Pin
The control interface is 5V tolerant, meaning that the control interface input signals CE, CL and DI as
well as MODE may have an input high level of 5V while DVDD is 3V. Input thresholds are determined
by DVDD.
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
In 3-wire mode, every rising edge of CL clocks in one data bit from the DI pin. A rising edge on CE
latches in a complete control word consisting of the last 16 bits. The 3-wire interface protocol is
shown in Figure 19.
latch
CE
CL
DI
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
control register address
control register data bits
Figure 19 3-wire SPI Compatible Interface
w
PP Rev 1.7 June 2004
21