WM8778 Datasheet, PDF (18/50 Pages) Wolfson Microelectronics plc – 24 BIT 192KHZ STEREO CODEC

WM8778
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LEFT JUSTIFIED MODE
In left justified mode, the MSB of DIN is sampled by the WM8778 on the first rising edge of
DACBCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and
changes on the same falling edge of ADCBCLK as ADCLRC and may be sampled on the rising edge
of ADCBCLK. ADCLRC and DACLRC are high during the left samples and low during the right
samples (Figure 12).
DACLRC/
ADCLRC
DACBCLK/
ADCBCLK
DIN/
DOUT
LEFT CHANNEL
123
MSB
n-2 n-1 n
LSB
1/fs
RIGHT CHANNEL
123
MSB
n-2 n-1 n
LSB
Figure 12 Left Justified Mode Timing Diagram
RIGHT JUSTIFIED MODE
In right justified mode, the LSB of DIN is sampled by the WM8778 on the rising edge of DACBCLK
preceding a DACLRC transition. The LSB of the ADC data is output on DOUT and changes on the
falling edge of ADCBCLK preceding a ADCLRC transition and may be sampled on the rising edge of
ADCBCLK. ADCLRC and DACLRC are high during the left samples and low during the right samples
(Figure 13).
1/fs
DACLRC/
ADCLRC
DACBCLK/
ADCBCLK
LEFT CHANNEL
DIN/
DOUT
123
MSB
n-2 n-1 n
LSB
Figure 13 Right Justified Mode Timing Diagram
RIGHT CHANNEL
123
MSB
n-2 n-1 n
LSB
w
PP Rev 1.7 June 2004
18