WM8778 Datasheet, PDF (10/50 Pages) Wolfson Microelectronics plc – 24 BIT 192KHZ STEREO CODEC

WM8778
ADCBCLK/
DACBCLK
DACLRC/
ADCLRC
DIN
DOUT
t_BCH
t_BCL
t_BCY
t_DS
t_DD
t_LRH
t_DH
t_LRSU
Product Preview
Figure 5 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25^oC, Slave Mode, fs = 48kHz, ADC/DACMCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
ADC/DACBCLK cycle time
tBCY
ADC/DACBCLK pulse width
tBCH
high
ADC/DACBCLK pulse width
tBCL
low
DACLRC/ADCLRC set-up
time to ADC/DACBCLK
rising edge
tLRSU
DACLRC/ADCLRC hold
tLRH
time from ADC/DACBCLK
rising edge
DIN set-up time to
tDS
DACBCLK rising edge
DIN hold time from
tDH
DACBCLK rising edge
DOUT propagation delay
tDD
from ADCBCLK falling edge
TEST CONDITIONS
MIN
TYP
MAX
UNIT
50
ns
20
ns
20
ns
10
ns
10
ns
10
ns
10
ns
0
10
ns
Table 3 Digital Audio Data Timing – Slave Mode
Note:
ADCLRC and DACLRC should be synchronous with MCLK, although the WM8778 interface is tolerant of phase variations
or jitter on these signals.
w
PP Rev 1.7 June 2004
10