WM8998 Datasheet, PDF (59/307 Pages) Wolfson Microelectronics plc – High Performance Audio Hub CODEC

Production Data
WM8998
DIGITAL CORE OUTPUTS
The digital core comprises multiple output paths. The output paths associated with AIF1, AIF2 and
AIF3 are illustrated in Figure 22. The output paths associated with OUT1, OUT2, OUT3, OUT4 and
OUT5 are illustrated in Figure 23. The output paths associated with the SLIMbus interface are
illustrated in Figure 24.
A 4-input mixer is associated with each of the AIFn or OUTn signal paths. The 4 input sources are
selectable in each case, and independent volume control is provided for each path. Note that there
are no mixers associated with the SLIMbus output paths.
The AIF1, AIF2 and AIF3 output mixer control registers (see Figure 22) are located at register
addresses R1792 (700h) through to R1935 (78Fh). The OUT1, OUT2, OUT3, OUT4 and OUT5 output
mixer control registers (see Figure 23) are located at addresses R1664 (680h) through to R1743
(06CFh). The SLIMbus output control registers (see Figure 24) are located at addresses R1984
(7C0h) through to R2025 (7E9h).
The full list of digital mixer control registers is provided in the “Register Map” section (Register R1600
through to R2920). Generic register definitions are provided in Table 7.
The *_SRCn registers select the input source(s) for the respective signal paths. Note that the selected
input source(s) must be configured for the same sample rate as the mixer to which they are
connected. Sample rate conversion functions are available to support flexible interconnectivity - see
“Asynchronous Sample Rate Converter (ASRC)” and “Isochronous Sample Rate Converter (ISRC)”.
The sample rate for the output signal paths is configured using the applicable OUT_RATE,
AIFn_RATE or SLIMTXn_RATE register - see Table 19. Note that sample rate conversion is required
when routing the output signal paths to any signal chain that is asynchronous and/or configured for a
different sample rate.
The WM8998 performs automatic checks to confirm that the SYSCLK frequency is high enough to
support the output mixer paths. If an attempt is made to enable an output mixer path, and there are
insufficient SYSCLK cycles to support it, then the attempt will be unsuccessful. (Note that any signal
paths that are already active will not be affected under these circumstances.)
The Underclocked Error condition can be monitored using the GPIO and/or Interrupt functions. See
“General Purpose Input / Output” and “Interrupts” for further details.
The status bits in Registers R1600 to R2920 indicate the status of each of the digital mixers. If an
Underclocked Error condition occurs, then these bits provide readback of which mixer(s) have been
successfully enabled.
w
PD, October 2014, Rev 4.0
59