WM8998 Datasheet, PDF (226/307 Pages) Wolfson Microelectronics plc – High Performance Audio Hub CODEC

WM8998
REGISTER BIT
ADDRESS
LABEL
3:0 FLL1_REFCLK_S
RC
R377
(0179h)
FLL1
Control 7
5:2 FLL1_GAIN [3:0]
R385
0 FLL1_SYNC_EN
(0181h)
A
FLL1
Synchroni
ser 1
R386
(0182h)
FLL1
Synchroni
ser 2
R387
(0183h)
FLL1
Synchroni
ser 3
R388
(0184h)
FLL1
Synchroni
ser 4
R389
(0185h)
FLL1
Synchroni
ser 5
9:0
15:0
15:0
10:8
FLL1_SYNC_N
[9:0]
FLL1_SYNC_TH
ETA [15:0]
FLL1_SYNC_LA
MBDA [15:0]
FLL1_SYNC_FR
ATIO [2:0]
DEFAULT
Production Data
DESCRIPTION
0000
0000
0
000h
FLL1 Clock source
0000 = MCLK1
0001 = MCLK2
0011 = SLIMCLK
0100 = FLL1
0101 = FLL2
1000 = AIF1BCLK
1001 = AIF2BCLK
1010 = AIF3BCLK
1100 = AIF1LRCLK
1101 = AIF2LRCLK
1110 = AIF3LRCLK
All other codes are Reserved
FLL1 Gain
0000 = 1
0001 = 2
0010 = 4
0011 = 8
0100 = 16
0101 = 32
0110 = 64
0111 = 128
1000 to 1111 = 256
FLL1 Synchroniser Enable
0 = Disabled
1 = Enabled
This should be set as the final step of the
FLL1 synchroniser enable sequence, ie.
after the other synchroniser registers have
been configured.
FLL1 Integer multiply for FSYNC
(LSB = 1)
0000h
0000h
000
FLL1 Fractional multiply for FSYNC
This field sets the numerator (multiply)
part of the FLL1_SYNC_THETA /
FLL1_SYNC_LAMBDA ratio.
Coded as LSB = 1.
FLL1 Fractional multiply for FSYNC
This field sets the denominator (dividing)
part of the FLL1_SYNC_THETA /
FLL1_SYNC_LAMBDA ratio.
Coded as LSB = 1.
FLL1 Synchroniser FVCO clock divider
000 = 1
001 = 2
010 = 4
011 = 8
1XX = 16
w
PD, October 2014, Rev 4.0
226