WM8998 Datasheet, PDF (184/307 Pages) Wolfson Microelectronics plc – High Performance Audio Hub CODEC

WM8998
Production Data
GPn_FN
DESCRIPTION
COMMENTS
1 = Speaker Shutdown completed (due to Overheat
Temperature or Short Circuit condition)
Table 76 GPIO Function Select (GPIO1, GPIO2, GPIO3, GPIO4)
GPn_FN
00h
01h
02h
03h
04h
DESCRIPTION
Button detect input / Logic
level output
IRQ1 Output
IRQ2 Output
OPCLK Clock Output
COMMENTS
No function
GPn_DIR = 0: GPIO pin logic level is set by GPn_LVL.
GPn_DIR = 1: Button detect or logic level input.
Interrupt (IRQ1) output
0 = IRQ1 not asserted
1 = IRQ1 asserted
Interrupt (IRQ2) output
0 = IRQ2 not asserted
1 = IRQ2 asserted
Configurable clock output derived from SYSCLK
05h
FLL1 Clock
Clock output from FLL1
06h
FLL2 Clock
Clock output from FLL2
08h
PWM1 Output
Configurable Pulse Width Modulation output PWM1
09h
PWM2 Output
Configurable Pulse Width Modulation output PWM2
3Dh
OPCLK Async Clock
Output
Configurable clock output derived from ASYNCCLK
Table 77 GPIO Function Select (GPIO5)
BUTTON DETECT (GPIO INPUT)
GPn_FN = 01h.
Button detect functionality can be selected on a GPIO pin by setting the respective GPIO registers as
described in “GPIO Control”. The same functionality can be used to support a Jack Detect input
function.
It is recommended to enable the GPIO input de-bounce feature when using GPIOs as button input or
Jack Detect input.
The GPn_LVL fields may be read to determine the logic levels on a GPIO input, after the selectable
de-bounce controls. Note that GPn_LVL is not affected by the GPn_POL bit.
The de-bounced GPIO signals are also inputs to the Interrupt control circuit. An interrupt event is
triggered on the rising and falling edges of the GPIO input. The associated interrupt bits are latched
once set; it can be polled at any time or used to control the IRQ signal. See “Interrupts” for more
details of the Interrupt event handling.
LOGIC ‘1’ AND LOGIC ‘0’ OUTPUT (GPIO OUTPUT)
GPn_FN = 01h.
The WM8998 can be programmed to drive a logic high or logic low level on a GPIO pin by selecting
the “GPIO Output” function as described in “GPIO Control”.
The output logic level is selected using the respective GPn_LVL bit. Note that the GPn_LVL registers
are ‘write only’ when the respective GPIO pin is configured as an output.
The polarity of the GPIO output can be inverted using the GPn_POL registers. If GPn_POL=1, then
the external output will be the opposite logic level to GPn_LVL.
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PD, October 2014, Rev 4.0
184