WM8998 Datasheet, PDF (171/307 Pages) Wolfson Microelectronics plc – High Performance Audio Hub CODEC

Production Data
WM8998
LOW POWER SLEEP CONFIGURATION
The WM8998 supports a low-power ‘Sleep’ mode, where most functions are disabled, and power
consumption is minimised. A selectable ‘Wake-Up’ event can be configured to return the device to full
operation and/or execute a specific response to the particular Wake-Up condition.
A Wake-Up event is triggered via hardware input pin(s); in typical applications, these inputs are
associated with jack insert (via the JACKDET analogue input) or external push-button detection (via
the GPIO5 digital input). A Wake-Up transition can also be triggered using the LDOENA pin to enable
LDO1 (assuming that DCVDD is supplied by LDO1).
The WM8998 enters Sleep mode when LDO1 is disabled, causing the DCVDD supply to be removed.
The AVDD, DBVDD1, and LDOVDD supplies must be present throughout the Sleep mode duration.
Note that it is assumed that DCVDD is supplied by LDO1; see the “Charge Pumps, Regulators and
Voltage Reference” for specific control requirements where DCVDD is not powered from LDO1.
SLEEP MODE
The WM8998 enters Sleep mode when LDO1 is disabled, causing the DCVDD supply to be removed.
(LDO1 can be controlled using the LDO1_ENA register bit, or using the LDOENA pin; both of these
controls must be de-asserted to disable the LDO.) The AVDD, DBVDD1, and LDOVDD supplies must
be present throughout the Sleep mode; under these conditions, and with LDO1 disabled, most of the
Digital Core (and control registers) are held in reset.
Note that it is assumed that DCVDD is supplied by LDO1; see the “Charge Pumps, Regulators and
Voltage Reference” for specific control requirements where DCVDD is not powered from LDO1.
The system clocks (SYSCLK, ASYNCCLK) are not required in Sleep mode, and the external clock
inputs (MCLKn) may be stopped, except as described below.
If de-bounce is enabled on any of the configured Wake-Up signals (JACKDET or GPIO5), then the
32kHz clock must be active during Sleep mode (see “Clocking and Sample Rates”). The 32kHz clock
must be derived from the MCLK2 pin in this case. The 32kHz clock must be configured using
CLK_32K_ENA and CLK_32K_SRC before Sleep mode is entered.
The MCLK2 frequency limit in Sleep mode (see “Signal Timing Requirements”) must be observed
before entering Sleep mode, and maintained until after Wake-Up.
Selected functions and control registers are maintained via an ‘Always-On’ internal supply domain in
Sleep mode. The ‘Always-On’ control registers are listed in Table 70. These registers are maintained
(ie. not reset) in Sleep mode.
Note that the Control Interface is not supported in Sleep mode. Read/Write access to the ‘Always-On’
registers is not possible in Sleep mode.
w
PD, October 2014, Rev 4.0
171