WM8940_07 Datasheet, PDF (53/85 Pages) Wolfson Microelectronics plc – Mono CODEC with Speaker Driver

Pre-Production
WM8940
REGISTER
ADDRESS
BIT
LABEL
2
DLRSWAP
1
ALRSWAP
R5
5
Companding
Control
WL8
Table 43 Audio Interface Control
DEFAULT
DESCRIPTION
0
Controls whether DAC data appears in
‘right’ or ‘left’ phases of FRAME clock:
0=DAC data appear in ‘left’ phase of
FRAME
1=DAC data appears in ‘right’ phase of
FRAME
0
Controls whether ADC data appears in
‘right’ or ‘left’ phases of FRAME clock:
0=ADC data appear in ‘left’ phase of
FRAME
1=ADC data appears in ‘right’ phase of
FRAME
0
8 Bit Word Length Enable
Only recommended for use with
companding
0=Word Length controlled by WL
1=8 bits
Note: Right Justified Mode will only operate with a maximum of 24 bits. If 32-bit mode is selected the
device will operate in 24-bit mode.
REGISTER
ADDRESS
R6
Clock
generation
control
BIT
LABEL
8
CLKSEL
7:5 MCLKDIV
4:2 BCLKDIV
0
MS
Table 44 Clock Control
DEFAULT
DESCRIPTION
1
Controls the source of the clock for all
internal operation:
0=MCLK
1=PLL output
010
Sets the scaling for either the MCLK or
PLL clock output (under control of
CLKSEL)
000=divide by 1
001=divide by 1.5
010=divide by 2
011=divide by 3
100=divide by 4
101=divide by 6
110=divide by 8
111=divide by 12
000
Configures the BCLK and FRAME output
frequency, for use when the chip is
master over BCLK.
000=divide by 1 (BCLK=MCLK)
001=divide by 2 (BCLK=MCLK/2)
010=divide by 4
011=divide by 8
100=divide by 16
101=divide by 32
110=reserved
111=reserved
0
Sets the chip to be master over FRAME
and BCLK
0=BCLK and FRAME clock are inputs
1=BCLK and FRAME clock are outputs
generated by the WM8940 (MASTER)
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Pre-Production, Rev 3.0, February 2007
53