WM8352 Datasheet, PDF (49/336 Pages) Wolfson Microelectronics plc – Wolfson AudioPlus™ Stereo CODEC with Power Management

Production Data
WM8352
12.3.1 SYSCLK CONTROL
The MCLK_SEL bit is used to select the source for SYSCLK. The source may be either directly from
the MCLK input or may be from the output of the FLL. If required, the selected source may be divided
by two, as determined by MCLK_DIV, as described in Table 8. For further details of the FLL, see
Section 12.4.
When the internal clock source is switched from one value to another using MCLK_SEL, the change
of source will only occur following a falling edge of the source signal that was originally selected. In
the case where the clock source is switched from FLL to MCLK, a suitable falling edge can be
ensured by disabling the FLL after selection of MCLK as the source.
The recommended sequence of actions to switch from FLL to MCLK source is as follows:
 Select MCLK as source (MCLK_SEL = 0)
 Disable FLL (FLL_ENA = 0)
 Disable FLL oscillator (FLL_OSC_ENA = 0)
Note that, as an alternative to the above sequence, a software reset may be used to re-select MCLK
as the default SYSCLK source.
The recommended sequence of actions to switch from MCLK to FLL source is as follows:
 Enable FLL oscillator (FLL_OSC_ENA = 1)
 Enable FLL (FLL_ENA = 1)
 Select FLL as source (MCLK_SEL = 1)
REGISTER
ADDRESS
R40 (28h)
Clock Control
1
BIT
LABEL
11 MCLK_SEL
8 MCLK_DIV
Table 8 SYSCLK Control
DEFAULT
DESCRIPTION
0
Selects source for SYSCLK to CODEC
0 = MCLK pin
1 = FLL
0
Selects MCLK division in slave (MCLK
input) mode:
0 = divide MCLK by 1
1 = divide MCLK by 2
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PD, February 2011, Rev 4.4
49