WM8352 Datasheet, PDF (207/336 Pages) Wolfson Microelectronics plc – Wolfson AudioPlus™ Stereo CODEC with Power Management

Production Data
WM8352
24.3.12 WAKE-UP INTERRUPTS
The first-level WKUP_INT interrupt comprises several second-level interrupts. After a system reset,
these indicate to the host processor why the reset occurred. Each wake-up interrupt has a status bit
in Register R31 and a mask bit in Register R30, as defined in Table 154.
ADDRESS
R31 (1Fh)
Comparator
Interrupt
Status
BIT
LABEL
6
WKUP_OFF_STATE_EINT
5
WKUP_HIB_STATE_EINT
4
WKUP_CONV_FAULT_EINT
3
WKUP_WDOG_RST_EINT
2
WKUP_GP_PWR_ON_EINT
1
WKUP_ONKEY_EINT
0
WKUP_GP_WAKEUP_EINT
R39 (27h)
Comparator
Interrupt
Status Mask
6:0 “IM_” + name of respective
bit in R31
Table 154 Wake-up Interrupts
DESCRIPTION
Indicates that the chip started from the
OFF state.
(Rising Edge triggered)
Note: This bit is cleared once read.
Indicated the chip started up from the
hibernate state.
(Rising Edge triggered)
Note: This bit is cleared once read.
Indicates the wakeup was caused by a
converter fault leading to the chip being
reset.
(Rising Edge triggered)
Note: This bit is cleared once read.
Indicates the wakeup was caused by a
watchdog heartbeat being missed, and
hence the chip being reset.
(Rising Edge triggered)
Note: This bit is cleared once read.
PWR_ON (Alternate GPIO function) pin
has been pressed for longer than
specified time.
(Rising Edge triggered)
Note: This bit is cleared once read.
ON key has been pressed for longer than
specified time.
(Rising Edge triggered)
Note: This bit is cleared once read.
WAKEUP (Alternate GPIO function) pin
has been pressed for longer than
specified time.
(Rising Edge triggered)
Note: This bit is cleared once read.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Each bit in R39 enables or masks the
corresponding bit in R31. The default
value for these bits is 0 (unmasked).
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PD, February 2011, Rev 4.4
207