WM8352 Datasheet, PDF (35/336 Pages) Wolfson Microelectronics plc – Wolfson AudioPlus™ Stereo CODEC with Power Management

Production Data
10.5 CONTROL INTERFACE TIMING
WM8352
Figure 18 Control Interface Timing - 2-wire Control Mode
Test Conditions
DCVDD = 1.8V, DBVDD = 3.3V, DGND = 0V, TA = +25^oC, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
SCLK Frequency
SCLK Low Pulse-Width
SCLK High Pulse-Width
Hold Time (Start Condition)
Setup Time (Start Condition)
Data Setup Time
SDATA, SCLK Rise Time
SDATA, SCLK Fall Time
Setup Time (Stop Condition)
Data Hold Time
Pulse width of spikes that will be suppressed
0
t1
1.3
t2
600
t3
600
t4
600
t5
100
t6
t7
t8
600
t9
tps
0
526
kHz
us
ns
ns
ns
ns
300
ns
300
ns
ns
900
ns
5
ns
w
PD, February 2011, Rev 4.4
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