WM8581_07 Datasheet, PDF (45/100 Pages) Wolfson Microelectronics plc – Multichannel CODEC with S/PDIF Transceiver

Production Data
WM8581
S/PDIF INTERFACES
The TX_CLKSEL register selects the clock for the S/PDIF Transmitter from ADCMCLK, PLLACLK,
PLLBCLK, or MCLK. The S/PDIF Receiver only uses PLLACLK. If the digital routing has been
configured such that the S/PDIF Transmitter is sourcing the S/PDIF Receiver, then PLLACLK is
automatically selected. The rate that the S/PDIF Transmitter operates at is determined by the S/PDIF
Tx Rate module. It calculates the rate based on the digital routing setup. When sourcing from the
S/PDIF Receiver, the SFRM_CLK is used in the rate calculation. When sourcing from the PAIF
Receiver, PAIFRX_LRCLK is used in the rate calculation. When sourcing from the SAIF Receiver,
SAIFRX_LRCLK is used in the rate calculation. When sourcing the ADC, the rate is determined by
either the PAIFTX_LRCLK (if the PAIF Tx also sources the ADC) or the ADC_RATE register.
Figure 28 S/PDIF Clock Selection
REGISTER BIT
ADDRESS
R8
5:4
LABEL
TX_CLKSEL
DEFAULT
01
Table 35 S/PDIF Transmitter Clock Control
DESCRIPTION
S/PDIF TX clock source
00 = ADCMLCK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
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PD Rev 4.0 April 2007
45