WM8581_07 Datasheet, PDF (35/100 Pages) Wolfson Microelectronics plc – Multichannel CODEC with S/PDIF Transceiver

Production Data
WM8581
INFINITE ZERO DETECT
Setting the IZD register bit will enable the internal Infinite Zero Detect function:
REGISTER ADDRESS BIT
R16
7
DAC CONTROL 2
10h
Table 21 IZD Register
LABEL
IZD
DEFAULT
0
DESCRIPTION
Infinite zero detection circuit control
and automute control
0 = Infinite zero detect automute
disabled
1 = Infinite zero detect automute
enabled
With IZD enabled, applying 1024 consecutive zero input samples to a stereo input channel on any
DAC will cause that stereo channel output to be muted. Mute will be removed as soon as either of
those stereo channels receives a non-zero input.
DAC DIGITAL VOLUME CONTROL
The DAC volume may also be adjusted in the digital domain using independent digital attenuation
control registers
REGISTER
BIT
LABEL
DEFAULT
ADDRESS
DESCRIPTION
R20
7:0
DIGITAL
ATTENUATION ₈
DACL 1
14h
LDA1[7:0]
UPDATE
11111111
(0dB)
Not latched
Digital Attenuation control for DAC1 Left Channel (DACL1) in 0.5dB
steps. See Table 23
Controls simultaneous update of all Attenuation Latches
0 = Store LDA1 in intermediate latch (no change to output)
1 = Apply LDA1 and update attenuation on all channels
R21
7:0
DIGITAL
ATTENUATION
DACR 1
8
15h
RDA1[6:0]
UPDATE
11111111
(0dB)
Not latched
Digital Attenuation control for DAC1 Right Channel (DACR1) in
0.5dB steps. See Table 23
Controls simultaneous update of all Attenuation Latches
0 = Store RDA1 in intermediate latch (no change to output)
1 = Apply RDA1 and update attenuation on all channels.
R22
7:0
DIGITAL
ATTENUATION
DACL 2
8
16h
LDA2[7:0]
UPDATE
11111111
(0dB)
Not latched
Digital Attenuation control for DAC2 Left Channel (DACL2) in 0.5dB
steps. See Table 23
Controls simultaneous update of all Attenuation Latches
0 = Store LDA2 in intermediate latch (no change to output)
1 = Apply LDA2 and update attenuation on all channels.
R23
7:0
DIGITAL
ATTENUATION
DACR 2
8
17h
RDA2[7:0]
UPDATE
11111111
(0dB)
Not latched
Digital Attenuation control for DAC2 Right Channel (DACR2) in
0.5dB steps. See Table 23
Controls simultaneous update of all Attenuation Latches
0 = Store RDA2 in intermediate latch (no change to output)
1 = Apply RDA2 and update attenuation on all channels.
R24
7:0
DIGITAL
ATTENUATION
DACL3
8
18h
LDA3[7:0]
UPDATE
11111111
(0dB)
Not latched
Digital Attenuation control for DAC3 Left Channel (DACL3) in 0.5dB
steps. See Table 23
Controls simultaneous update of all Attenuation Latches
0 = Store LDA3 in intermediate latch (no change to output)
1 = Apply LDA3 and update attenuation on all channels.
R25
7:0
DIGITAL
ATTENUATION
DACR3
8
19h
RDA3[7:0]
UPDATE
11111111
(0dB)
Not latched
Digital Attenuation control for DAC3 Right Channel (DACR3) in
0.5dB steps. See Table 23
Controls simultaneous update of all Attenuation Latches
0 = Store RDA3 in intermediate latch (no change to output)
1 = Apply RDA3 and update attenuation on all channels.
w
PD Rev 4.0 April 2007
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