WM8581_07 Datasheet, PDF (34/100 Pages) Wolfson Microelectronics plc – Multichannel CODEC with S/PDIF Transceiver

WM8581
Production Data
DAC OUTPUT CONTROL
The DAC output control word determines how the left and right inputs to the audio interface are
applied to the left and right DACs:
REGISTER ADDRESS BIT
R16
3:0
DAC CONTROL 2
10h
LABEL
PL[3:0]
DEFAULT
1001
DESCRIPTION
PL[3:0] Left O/P Right O/P
0000
Mute
Mute
0001
Left
Mute
0010
Right
Mute
0011
(L+R)/2
Mute
0100
Mute
Left
0101
Left
Left
0110
Right
Left
0111
(L+R)/2
Left
1000
Mute
Right
1001
Left
Right
1010
Right
Right
1011
(L+R)/2
Right
1100
1101
Mute
Left
(L+R)/2
(L+R)/2
1110
Right
(L+R)/2
1111
(L+R)/2 (L+R)/2
Table 19 DAC Attenuation Register (PL)
ZERO FLAG OUTPUT
Each DAC channel has a “zero detect circuit” which detects when 1024 consecutive zero samples
have been input. Should both channels of a DAC indicate a zero-detect (or if either DACPD or
DMUTE is set for that DAC), then the Zero Flag for that DAC is asserted. The DZFM register bits
determine which Zero Flag is visible on the MUTE and GPO pins.
REGISTER ADDRESS BIT
LABEL
R16
6:4 DZFM[2:0]
DAC CONTROL 2
10h
Table 20 DZFM Register
DEFAULT
000
DESCRIPTION
Selects the source for ZFLAG
000 – All DACs Zero Flag
001 – DAC1 Zero Flag
010 – DAC2 Zero Flag
011 – DAC3 Zero Flag
100 – DAC4 Zero Flag
101 – ZFLAG = 0
110 – ZFLAG = 0
111 – ZFLAG = 0
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PD Rev 4.0 April 2007
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