WM8953 Datasheet, PDF (44/100 Pages) Wolfson Microelectronics plc – Low Power Stereo ADC with PLL and TDM Interface

WM8953
Production Data
BUTTON CONTROL
The WM8953 GPIO supports button control detection with full status readback for up to four inputs
(and one IRQ output). All inputs are latched at the IRQ Register, with de-bounce available for normal
operation. De-bouncing may be disabled in order to allow the device to respond to wake-up events
while the processor is disabled and is unable to provide a clock for de-bouncing.
To enable button control and accessory detection, the following register settings are required:
• LMN3 = 0 (only required if using GPI7)
• RMN3 = 0 (only required if using GPI8)
• AIF_TRIS = 0
• GPIOn_SEL = 0000 for each required GPIO button input
Programmable pull-up and pull-down resistors are available on GPIO3, GPIO4 and GPIO5. These
should be set according to the external circuit configuration. Note that pull-up and pull-down resistors
are not available on the GPI7 and GPI8 input pins. Note that the analogue input paths to GPI7 and
GPI8 must be disabled as described above when using these as digital inputs.
In this application, one or more of the GPIO pins may be configured as an Interrupt event if desired.
This is controlled by the GPIOn_IRQ_ENA bits described in Table 21. The GPIO Pin status fields
contained in the IRQ Register (R18) may be read at any time or else in response to an Interrupt
event. See Table 30 for more details of the Interrupt function.
An example configuration of the button control GPIO function is illustrated in Figure 21.
Figure 21 Example of Button Control Using GPIO Pins
Note:
•
•
The GPIOs 3, 4, and 5 are referenced to DBVDD
The GPIs 7 and 8 are referenced to AVDD
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PD, January 2009, Rev 4.0
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