WM8953 Datasheet, PDF (18/100 Pages) Wolfson Microelectronics plc – Low Power Stereo ADC with PLL and TDM Interface

WM8953
AUDIO INTERFACE TIMING – SLAVE MODE
Production Data
Figure 4 Digital Audio Data Timing – Slave Mode
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=3.3V, DGND=AGND=0V, TA=+25^oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless
otherwise stated.
PARAMETER
Audio Data Input Timing Information
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
ADCLRC set-up time to BCLK rising edge
ADCLRC hold time from rising edge
ADCDAT propagation delay from BCLK falling edge
Note:
SYMBOL
tBCY
tBCH
tBCL
tLRSU
tLRH
tDD
MIN
TYP
MAX
UNIT
50
ns
20
ns
20
ns
20
ns
10
ns
20
ns
BCLK period should always be greater than or equal to MCLK period.
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PD, January 2009, Rev 4.0
18