WM8912 Datasheet, PDF (40/128 Pages) Wolfson Microelectronics plc – Ultra Low Power DAC with Headphone Driver for Portable Audio Applications

WM8912
Production Data
REGISTER BIT
ADDRESS
LABEL
DEFAULT
DESCRIPTION
3
HPR_RMV_SHO
RT
0
Removes HPR short
0 = HPR short enabled
1 = HPR short removed
For normal operation, this bit should
be set as the final step of the HPR
Enable sequence.
2 HPR_ENA_OUTP
0
Enables HPR output stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the DC offset
cancellation has been scheduled.
1
HPR_ENA_DLY
0
Enables HPR intermediate stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the output signal path
has been configured, and before DC
offset cancellation is scheduled. This
bit should be set with at least 20us
delay after HPR_ENA.
0
HPR_ENA
0
Enables HPR input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set as the first step of the HPR
Enable sequence.
R94 (5Eh)
Analogue
Lineout 0
7
LINEOUTL_RMV
_SHORT
0
Removes LINEOUTL short
0 = LINEOUTL short enabled
1 = LINEOUTL short removed
For normal operation, this bit should
be set as the final step of the
LINEOUTL Enable sequence.
6 LINEOUTL_ENA_
0
Enables LINEOUTL output stage
OUTP
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the DC offset
cancellation has been scheduled.
5 LINEOUTL_ENA_
0
Enables LINEOUTL intermediate
DLY
stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the output signal path
has been configured, and before DC
offset cancellation is scheduled. This
bit should be set with at least 20us
delay after LINEOUTL_ENA.
4
LINEOUTL_ENA
0
Enables LINEOUTL input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set as the first step of the
LINEOUTL Enable sequence.
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PD, Rev 4.0, September 2010
40