WM1811A Datasheet, PDF (257/328 Pages) Wolfson Microelectronics plc – Multi-Channel Audio Hub CODEC for Smartphones

Production Data
REGISTER BIT
ADDRESS
2:0
LABEL
AIF1ADC_DIV
[2:0]
Register 0201h AIF1 Clocking (2)
DEFAULT
DESCRIPTION
WM1811A
000
Selects the AIF1 output path sample rate relative to the AIF1 input path
sample rate.
This field should only be changed from default in modes where the AIF1
output path sample rate is slower than the AIF1 input path sample rate.
000 = Divide by 1
001 = Divide by 1.5
010 = Divide by 2
011 = Divide by 3
100 = Divide by 4
101 = Divide by 5.5
110 = Divide by 6
111 = Reserved
REGISTER BIT
ADDRESS
R516 (0204h) 4:3
AIF2
Clocking (1)
LABEL
AIF2CLK_SRC
[1:0]
2
AIF2CLK_INV
1
AIF2CLK_DIV
0
AIF2CLK_ENA
Register 0204h AIF2 Clocking (1)
DEFAULT
00
AIF2CLK Source Select
00 = MCLK1
01 = MCLK2
10 = FLL1
11 = FLL2
0
AIF2CLK Invert
0 = AIF2CLK not inverted
1 = AIF2CLK inverted
0
AIF2CLK Divider
0 = AIF2CLK
1 = AIF2CLK / 2
0
AIF2CLK Enable
0 = Disabled
1 = Enabled
DESCRIPTION
REGISTER BIT
ADDRESS
R520 (0208h) 4
Clocking (1)
LABEL
TOCLK_ENA
3 AIF1DSPCLK_EN
A
2 AIF2DSPCLK_EN
A
1 SYSDSPCLK_EN
A
0
SYSCLK_SRC
Register 0208h Clocking (1)
w
DEFAULT
DESCRIPTION
0
Slow Clock (TOCLK) Enable
0 = Disabled
1 = Enabled
This clock is required for zero-cross timeout.
0
AIF1 Processing Clock Enable
0 = Disabled
1 = Enabled
0
AIF2 Processing Clock Enable
0 = Disabled
1 = Enabled
0
Digital Mixing Processor Clock Enable
0 = Disabled
1 = Enabled
0
SYSCLK Source Select
0 = AIF1CLK
1 = AIF2CLK
PD, November 2013, Rev 4.1
257