WM1811A Datasheet, PDF (185/328 Pages) Wolfson Microelectronics plc – Multi-Channel Audio Hub CODEC for Smartphones

Production Data
WM1811A
REGISTER BIT
ADDRESS
LABEL
DEFAULT
DESCRIPTION
R529
(0211h)
7:4 AIF2_SR
AIF2 Rate
1000
Selects the AIF2 Sample Rate (fs)
0000 = 8kHz
0001 = 11.025kHz
0010 = 12kHz
0011 = 16kHz
0100 = 22.05kHz
0101 = 24kHz
0110 = 32kHz
0111 = 44.1kHz
1000 = 48kHz
1001 = 88.2kHz
1010 = 96kHz
All other codes = Reserved
Note that 88.2kHz and 96kHz modes are
supported for AIF2 input (DAC playback) only.
3:0 AIF2CLK_RAT
E
0011
Selects the AIF2CLK / fs ratio
0000 = Reserved
0001 = 128
0010 = 192
0011 = 256
0100 = 384
0101 = 512
0110 = 768
0111 = 1024
1000 = 1408
1001 = 1536
All other codes = Reserved
Table 111 AIF2 Clocking Configuration
MISCELLANEOUS CLOCK CONTROLS
SYSCLK provides clocking for many of the WM1811A functions. SYSCLK clock is required to support
DSP Core functions and also the Charge Pump, Class D switching amplifier, DC servo control and
other internal functions.
The SYSCLK_SRC register is used to select the SYSCLK source. The source may be AIF1CLK or
AIF2CLK, as illustrated in Figure 68. Note that the bandwidth of the digital audio mixing paths will be
determined by the sample rate of whichever AIF is selected as the SYSCLK source. When using only
one audio interface, the active interface should be selected as the SYSCLK source. For best audio
performance when using AIF1 and AIF2 simultaneously, the SYSCLK source must select the AIF with
the highest sample rate (AIFn_SR).
The AIF1 DSP processing clock is derived from SYSCLK, and enabled by AIF1DSPCLK_ENA.
The AIF2 DSP processing clock is derived from SYSCLK, and enabled by AIF2DSPCLK_ENA.
The clocking of the WM1811A ADC, DAC, digital mixer and digital microphone functions is enabled by
setting SYSDSPCLK_ENA. See “Digital Microphone Interface” for details of the DMICCLK frequency.
Two modes of ADC / Digital Microphone operation can be selected using the ADC_OSR128 bit. This
bit is enabled by default, giving best audio performance. De-selecting this bit provides a low power
alternative setting.
A high performance mode of DAC operation can be selected by setting the DAC_OSR128 bit. When
the DAC_OSR128 bit is set, the audio performance is improved, but power consumption is also
increased.
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PD, November 2013, Rev 4.1
185