WM1811A Datasheet, PDF (126/328 Pages) Wolfson Microelectronics plc – Multi-Channel Audio Hub CODEC for Smartphones

WM1811A
REGISTER
ADDRESS
R37 (0025h)
ClassD
BIT
LABEL
5:3 SPKOUTL_BOOST[
2:0]
2:0 SPKOUTR_BOOST[
2:0]
R1825
(0721h)
Pull Control
(2)
1 SPKMODE_PU
Table 72 Speaker Mode and Boost Control
DEFAULT
Production Data
DESCRIPTION
000
(1.0x)
000
(1.0x)
1
Left Speaker Gain Boost
000 = 1.00x boost (+0dB)
001 = 1.19x boost (+1.5dB)
010 = 1.41x boost (+3.0dB)
011 = 1.68x boost (+4.5dB)
100 = 2.00x boost (+6.0dB)
101 = 2.37x boost (+7.5dB)
110 = 2.81x boost (+9.0dB)
111 = 3.98x boost (+12.0dB)
Right Speaker Gain Boost
000 = 1.00x boost (+0dB)
001 = 1.19x boost (+1.5dB)
010 = 1.41x boost (+3.0dB)
011 = 1.68x boost (+4.5dB)
100 = 2.00x boost (+6.0dB)
101 = 2.37x boost (+7.5dB)
110 = 2.81x boost (+9.0dB)
111 = 3.98x boost (+12.0dB)
SPKMODE Pull-up enable
0 = Disabled
1 = Enabled
Clocking of the Class D output driver is derived from SYSCLK. The clocking frequency division is
configured automatically, according to the AIFn_SR and AIFnCLK_RATE registers. (See “Clocking
and Sample Rates” for further details of the system clocks and control registers.)
The Class D switching clock is enabled whenever SPKOUTL_ENA or SPKOUTR_ENA is set. The
frequency is as described in Table 73.
When AIF1CLK is selected as the SYSCLK source (SYSCLK_SRC = 0), then the Class D clock
frequency is controlled by the AIF1_SR and AIF1CLK_RATE registers.
When AIF2CLK is selected as the SYSCLK source (SYSCLK_SRC = 1), then the Class D clock
frequency is controlled by the AIF2_SR and AIF2CLK_RATE registers.
The applicable clocks (SYSCLK, AIF1CLK or AIF2CLK) must be present and enabled when using the
speaker outputs in Class D mode. The presence of a suitable clock is automatically detected by the
WM1811A; if the clock signal is absent, then the speaker outputs will be disabled.
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PD, November 2013, Rev 4.1
126