WM1811A Datasheet, PDF (186/328 Pages) Wolfson Microelectronics plc – Multi-Channel Audio Hub CODEC for Smartphones

WM1811A
Production Data
A clock is required for the Charge Pump circuit when the ground-referenced headphone outputs
(HPOUT1L and HPOUT1R) are enabled. The Charge Pump clock is derived from SYSCLK whenever
the Charge Pump is enabled. The Charge Pump clock division is configured automatically.
A clock is required for the Class D speaker driver circuit when the speaker outputs (SPKOUTL and
SPKOUTR) are enabled. The Class D clock is derived from SYSCLK whenever these outputs are
enabled in Class D mode. The Class D clock division is configured automatically. See “Analogue
Outputs” for details of the Class D switching frequency.
A clock output (OPCLK) derived from SYSCLK may be output on a GPIO pin. This clock is enabled by
register big OPCLK_ENA, and its frequency of this clock is controlled by OPCLK_DIV. See General
Purpose Input/Output” to configure a GPIO pin for this function.
A slow clock (TOCLK) is derived internally in order to control volume update timeouts when the zero-
cross option is selected. This clock is enabled by register bit TOCLK_ENA, and its frequency is
controlled by TOCLK_DIV.
A de-bounce control is provided for GPIO inputs and for other functions that may be selected as GPIO
outputs. The de-bounced clock frequency is controlled by DBCLK_DIV.
The WM1811A generates a 256kHz clock for internal functions; TOCLK and DBCLK are derived from
this 256kHz clock. In order to generate this clock correctly when SYSCLK_SRC = 0, valid settings are
required for AIF1_SR and AIF1CLK_RATE. To generate this clock correctly when SYSCLK_SRC = 1,
valid settings are required for AIF2_SR and AIF2CLK_RATE.
The WM1811A Clocking is illustrated in Figure 68.
Figure 68 System Clocking
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PD, November 2013, Rev 4.1
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