W83194R-58A Datasheet, PDF (9/13 Pages) Winbond – 100MHZ AGP CLOCK FOR VIA CHIPSET

W83194R-58A
PRELIMINARY
8.3.2 Register 1 : CPU , 48/24 MHz Clock Register (1 = Active, 0 = Inactive)
Bit @PowerUp Pin
Description
7
1
- 0 = 0.5% down type spread, overrides Byte0-bit7.
1= Center type spread.
6
1
- Reserved
5
1
- Reserved
4
1
- Reserved
3
1
40 CPUCLK3 (Active / Inactive)
2
1
41 CPUCLK2 (Active / Inactive)
1
1
43 CPUCLK1 (Active / Inactive)
0
1
44 CPUCLK0 (Active / Inactive)
8.3.3 Register 2: PCI Clock Register (1 = Active, 0 = Inactive)
Bit @PowerUp Pin
Description
7
x
- Reserved
6
1
7 PCICLK_F (Active / Inactive)
5
1
15 AGP0 (Active / Inactive)
4
1
14 PCICLK4 (Active / Inactive)
3
1
12 PCICLK3 (Active / Inactive)
2
1
11 PCICLK2 (Active / Inactive)
1
1
10 PCICLk1 (Active / Inactive)
0
1
8 PCICLK0 (Active / Inactive)
Publication Release Date: Nov. 1999
-9-
Revision 0.30