W83194R-58A Datasheet, PDF (2/13 Pages) Winbond – 100MHZ AGP CLOCK FOR VIA CHIPSET

W83194R-58A
3.0 BLOCK DIAGRAM
PLL2
~
X1
XTAL
X2
OSC
¡Ò₂
STOP
*FS(0:2) ³
*MODE
CPU3.3#_2.5
*SD_SEL#
CPU_STOP#
PCI_STOP#
*SDATA
*SCLK
PLL1
Spread
Spectrum
STOP
CPU_STOP#
LATCH
~⁵
POR
PCI
clock STOP
Divder
Control
Logic
Config.
Reg.
PCI_STOP#
PRELIMINARY
48MHz
24MHz
REF(0:1
2)
AGP(0:1)
2
CPUCLK(0:3)
4
SDRAM(0:11)
12
3
PCICLK(0:4)
5
PCICLK_F
4.0 PIN CONFIGURATION
Publication Release Date: Nov. 1999
-2-
Revision 0.30