W83194R-58A Datasheet, PDF (5/13 Pages) Winbond – 100MHZ AGP CLOCK FOR VIA CHIPSET

W83194R-58A
5.2 CPU, SDRAM, PCI Clock Outputs, continued
SYMBOL
PIN
PCICLK 0 / *FS2
8
PCICLK [ 1:4 ]
10,11,12,13
PRELIMINARY
I/O
I/O
OUT
FUNCTION
Latched input for FS2 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
PCI clock during normal operation.
Low skew (< 250ps) PCI clock outputs.
5.3 I²C Control Interface
SYMBOL
PIN
SDATA
23
SDCLK
24
I/O
FUNCTION
I/O Serial data of I²C 2-wire control interface
IN Serial clock of I²C 2-wire control interface
5.4 Fixed Frequency Outputs
SYMBOL
PIN
REF0 / CPU3.3#_2.5
2
REF1 /*SD_SEL#
46
24MHz / *MODE
25
48MHz / *FS0
26
I/O
FUNCTION
I/O Internal 250kΩ pull-up.
Latched input for CPU3.3#_2.5 at initial power up.
Reference clock during normal operation.
Latched high - Vddq2b = 2.5V
Latched low - Vddq2b = 3.3V
I/O Internal 250kΩ pull-up.
Latched input at Power On selects either
CPU(SDSEL=1) or AGP(SD_SEL=0) frequencies for
SDRAM clock outputs.
I/O Internal 250kΩ pull-up.
Latched input for MODE at initial power up. 24MHz
output for super I/O during normal operation.
I/O Internal 250kΩ pull-up.
Latched input for FS0 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks. 48MHz output for USB during normal
operation.
Publication Release Date: Nov. 1999
-5-
Revision 0.30