W83637HF_06 Datasheet, PDF (89/151 Pages) Winbond – LPC I/O

W83637HF/HG
Receiver Buffer Register (RBR at base address + 0 when BDLAB = 0, read only)
This register is the access port for receiver FIFO. It is active when Smart Card interface is in input
mode with SCIODIR (bit 1 of ECR at base address + 7) set to "1". The depth of receiver FIFO is 16
bytes.
7 6 5 4 32 1 0
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 7 ~ bit 0: Access port for receiver FIFO.
Receiver Buffer Register (RBR at base address + 0 when BDLAB = 0, read only)
This register is the access port for transmitter FIFO. It is active when Smart Card interface is in output
mode with SCIODIR (bit 1 of ECR at base address + 7) set to "0". The depth of transmitter FIFO is 16
bytes.
7 6 5 4 32 1 0
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 7 ~ bit 0: Access port for receiver FIFO.
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Publication Release Date: March, 2006
Revision 1.6